Substrate Dicing Patents (Class 438/33)
  • Patent number: 9577154
    Abstract: A light emitting chip includes a light emitting unit, a eutectic layer and a surface passivation layer. The eutectic layer has a first surface and a second surface opposite to each other. The light emitting chip connects to the first surface of the eutectic layer. The surface passivation layer covers the second surface of the eutectic layer. A material of the surface passivation layer includes at least a metal of an oxidation potential from ?0.2 volts to ?1.8 volts.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: February 21, 2017
    Assignee: Genesis Photonics Inc.
    Inventors: Yu-Yun Lo, Yi-Fan Li, Chih-Ling Wu, Yi-Ru Huang, Jing-En Huang, Shao-Ying Ting
  • Patent number: 9520697
    Abstract: A method for manufacturing a multi-emitter laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: December 13, 2016
    Assignee: SORAA LASER DIODE, INC.
    Inventors: Dan Steigerwald, Melvin McLaurin, Eric Goutain, Alexander Sztein, Po Shan Hsu, Paul Rudy, James W. Raring
  • Patent number: 9508899
    Abstract: A light emitting element manufacturing method includes a wafer preparing process of preparing the semiconductor wafer, and a wafer dividing process of dividing the semiconductor wafer. In the wafer dividing process, in a vertical dividing region, a line position shifted by a predetermined distance from a center line of the vertical dividing region in a width direction to one side in the width direction is taken as the cutting start point to divide the semiconductor wafer.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: November 29, 2016
    Assignee: NICHIA CORPORATION
    Inventor: Akinori Yoneda
  • Patent number: 9431589
    Abstract: A packaged LED device having a textured encapsulant that is conformal with a mount surface on which at least one LED chip is disposed. The textured encapsulant, which can be textured using an additive or subtractive process, is applied to the LED either prior to or during packaging. The encapsulant includes at least one textured surface from which light is emitted. The textured surface helps to reduce total internal reflection within the encapsulant, improving the extraction efficiency and the color temperature uniformity of the output profile. Several chips can be mounted beneath a single textured encapsulant. A mold having irregular surfaces can be used to form multiple encapsulants over many LEDs simultaneously.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: August 30, 2016
    Assignee: CREE, INC.
    Inventors: Ban P. Loh, Chenhua You, Bernd Keller, Nathaniel O. Cannon, Mitch Jackson, Ernest W. Combs
  • Patent number: 9385268
    Abstract: A method of manufacturing semiconductor chips includes: forming grooves on a front face side of a substrate; and forming grooves on a back face side of the substrate as defined herein, and in manufacturing conditions in which a variation range of a top section of the cutting member having a tapered tip end shape with no top face in the groove width direction changes from a range included in the groove on the front face side to a range away from the groove on the front face side as wear of the cutting member advances, the use of the cutting member is stopped before the variation range changes from the range included in the groove on the front face side to the range away from the groove on the front face side.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: July 5, 2016
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Takeshi Minamiru, Michiaki Murata, Kenji Yamazaki, Tsutomu Otsuka
  • Patent number: 9368939
    Abstract: A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: June 14, 2016
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, James W. Raring, Alexander Sztein, Po Shan Hsu
  • Patent number: 9306141
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer; a p-side electrode provided on the second surface of the semiconductor layer in a region including the light emitting layer; an n-side electrode provided on the second surface of the semiconductor layer in a region not including the light emitting layer; an insulating film being more flexible than the semiconductor layer, the insulating film provided on the second surface and a side surface of the semiconductor layer, and the insulating film having a first opening reaching the p-side electrode and a second opening reaching the n-side electrode; a p-side interconnection layer provided on the insulating film and connected to the p-side electrode; and an n-side interconnection layer provided on the insulating film and connected to the n-side electrode.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Hamasaki, Akihiro Kojima, Yoshiaki Sugizaki
  • Patent number: 9276174
    Abstract: A semiconductor light emitting device which can control of current density and can optimize current density and in which a rise in luminosity is possible, and a fabrication method of the semiconductor light emitting device are provided.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: March 1, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Masakazu Takao, Kazuhiko Senda
  • Patent number: 9263397
    Abstract: A method for providing alignment in a die picking process may include aligning a semiconductor wafer based on a reference die, forming an indicator line relative to the reference die by picking a number of dice along a line extending across the wafer, and using the reference line to monitor a position of the picking machine relative to the wafer. A die attach machine may include a control system for automatically implementing such method.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: February 16, 2016
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Matthew Gibson, Prem Na-Namchiew, Ekgachai Kenganantanon, Mathew Bunker
  • Patent number: 9236710
    Abstract: A method of manufacturing a semiconductor laser element including: preparing a wafer; forming first grooves on at least one of an upper surface and a lower surface of the wafer, each of the first grooves being spaced apart from the optical waveguide formed in the wafer and extending in a direction intersecting the optical waveguide in a plan view; forming second grooves on the one of the upper surface and the lower surface of the wafer, each of the second grooves extending in a direction intersecting a straight line extended from each of the first grooves, and each of the second grooves having a smooth surface compared with the first grooves; dividing the wafer along the first grooves to obtain a plurality of laser bars; and dividing the laser bars in a direction intersecting an extending direction of the first grooves to obtain the semiconductor laser elements.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: January 12, 2016
    Assignee: NICHIA CORPORATION
    Inventors: Shingo Tanisaka, Hiroki Koizumi
  • Patent number: 9214608
    Abstract: A luminescence diode arrangement includes a first luminescence diode chip, a second luminescence diode chip and a luminescence conversion element, wherein the first luminescence diode chip emits blue light, the second luminescence diode chip contains a semiconductor layer sequence that emits greens light, the luminescence conversion element converts part of the blue light emitted by the first luminescence diode chip into red light, and the luminescence diode arrangement emits mixed light containing blue light of the first luminescence diode chip, green light of the second luminescence diode chip and red light of the luminescence conversion element.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: December 15, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Thorsten Kunz, Stephan Kaiser
  • Patent number: 9209351
    Abstract: A method for manufacturing a light emitting element includes: preparing a wafer that has a substrate in which a first main face is provided with a plurality of convex components; and dividing the wafer along first dividing lines and second dividing lines. The convex components are in the form of circular cones or truncated circular cones, each of which having a circular bottom face and a side face that is connected to the bottom face, and disposed regularly so that a plurality of bounded regions are present around the convex components, and a shortest distance between the convex components and the centers of the bounded regions is less than a radius of the bottom faces of the convex components. The first and second dividing lines extend in a direction that intersects straight lines that link the centers of the plurality of bounded regions around a single convex component.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: December 8, 2015
    Assignee: NICHIA CORPORATION
    Inventor: Hiroaki Tamemoto
  • Patent number: 9185791
    Abstract: The present invention relates to a manufacturing method of a printing circuit board. The manufacturing method mainly includes: forming one or more cylindrical micro-radiators by cutting a high conductive and electrical insulating substrate according to predetermined size; manufacturing one or more mounting holes in copper clad plates and prepregs; embedding the cylindrical micro-radiators into the mounting holes. The present invention combines the micro-radiator with high thermal conductivity and traditional stiffness printing circuit board. The printing circuit board with micro-radiators has the advantages of high thermal conductivity and stable heat transfer, and also has the advantages of routing flexibility and reliable electrical connections.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: November 10, 2015
    Assignee: RAYBEN TECHNOLOGIES (ZHUHAI) LIMITED
    Inventor: Zheng Wang
  • Patent number: 9171760
    Abstract: A method of manufacturing a semiconductor device includes: forming electrodes on a first major surface of a semiconductor substrate having first and second major surfaces facing in opposite directions; and forming a cleavage-inducing pattern on the first major surface of the semiconductor substrate. The cleavage-inducing pattern extends over a target cleavage position located between the electrodes, has a recess extending over the target cleavage position, and is made of a material different from the material of the semiconductor substrate. The method includes forming a scribed groove in the second major surface of the semiconductor substrate and in a position facing the target cleavage position; and cleaving the semiconductor substrate having the scribed groove and the cleavage-inducing pattern by applying pressure, through a cleaving blade, to the first major surface of the semiconductor substrate.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: October 27, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Chikara Watatani, Masato Negishi
  • Patent number: 9142734
    Abstract: An emitter includes a light source and a separately formed conversion material region with conversion particles. The light source is capable of emitting light along a plurality of light paths extending through the conversion material region where at least some of the light can be absorbed by the conversion particles. The light from the light source and the light re-emitted from the conversion particles combine to provide a desired color of light. Each light path extends through a substantially similar amount of conversion particles so that the desired color of light has a substantially uniform color and intensity along each light path.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: September 22, 2015
    Assignee: Cree, Inc.
    Inventors: James Ibbetson, Eric Tarsa
  • Patent number: 9136255
    Abstract: A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: September 15, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-Kyoung Seo, Eun-Jin Choi
  • Patent number: 9076923
    Abstract: A method for manufacturing a light-emitting device comprising the steps of: providing a first substrate, a chip area, and a street area; forming a light-emitting structure on the first substrate; forming a conductive structure between the first substrate and the light-emitting structure; removing a part of the light-emitting structure in the street area to expose a sidewall of the light-emitting structure in the chip area; forming a first passivation layer on the light-emitting structure in the chip area; forming a second passivation layer on the conductive structure in the street area, on the sidewalls of the light-emitting structure, and on the sidewalls of the first passivation layer; forming a through-hole in the first passivation layer, and forming an electrode in the through-hole.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: July 7, 2015
    Assignee: EPISTAR CORPORATION
    Inventors: Cheng-Hsien Li, Chi-Hao Huang, Hsin-Hsiung Huang
  • Publication number: 20150144971
    Abstract: Thick metal pillars are formed upon light emitting dies while the dies are still on their supporting wafer. A molding compound is applied to fill the space between the pillars on each die, and contact pads are formed atop the pillars. The metal pillars provide electrical contact between the contact pads and the electrical contacts of each light emitting die. The metal pillars maybe formed upon an upper metal layer of each die, and this upper metal layer maybe patterned to provide connections to individual elements within the die.
    Type: Application
    Filed: June 4, 2013
    Publication date: May 28, 2015
    Inventors: Jipu Lei, Stefano Schiaffino, ALexander H. Nickel, Mooi Guan Ng, Grigoriy Basin, Salman Akram
  • Publication number: 20150144968
    Abstract: A method of dicing semiconductor devices includes depositing a continuous first layer over the substrate, such that the first layer imparts a compressive stress to the substrate, and etching grooves in the first layer to increase local stress at the grooves compared to stress at the remainder of the first layer located over the substrate. The method also includes generating a pattern of defects in the substrate with a laser beam, such that a location of the defects in the pattern of defects substantially corresponds to a location of at least some of the grooves in the in the first layer, and applying pressure to the substrate to dice the substrate along the grooves.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Inventors: Scott Brad Herner, Linda Romano, Daniel Bryce Thompson, Martin Schubert
  • Patent number: 9040389
    Abstract: In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Gunther Mackh, Maria Heidenblut, Adolf Koller, Anatoly Sotnikov
  • Publication number: 20150140710
    Abstract: A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.
    Type: Application
    Filed: December 3, 2014
    Publication date: May 21, 2015
    Inventors: Melvin McLaurin, James W. Raring, Alexander Sztein, Po Shan Hsu
  • Publication number: 20150140711
    Abstract: A method according to embodiments of the invention includes providing a wafer comprising a semiconductor structure grown on a growth substrate. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. The wafer includes trenches defining individual semiconductor devices. The trenches extend through an entire thickness of the semiconductor structure to reveal the growth substrate. The method further includes forming a thick conductive layer on the semiconductor structure. The thick conductive layer is configured to support the semiconductor structure when the growth substrate is removed. The method further includes removing the growth substrate.
    Type: Application
    Filed: May 8, 2013
    Publication date: May 21, 2015
    Inventors: Jipu Lei, Alexander H. Nickel, Stefano Schiaffino, Grigoriy Basin
  • Patent number: 9034733
    Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 19, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
  • Patent number: 9036671
    Abstract: A method for fabricating a group-III nitride semiconductor laser device stably supplies laser cavity mirrors having a low lasing threshold current through the use of a semi-polar plane. A blade 5g is forced down through a first region ER1 to keep the first region ER1 squeezed between a support member H2 and a movable member H1 together with a part of a protective sheet TF in contact with the first region ER1 while the tension generated in the area of the protective sheet TF in contact with the first region ER1 with the movable member H1 increases until the semi-polar principal surface SF at an end face EG1 of the first region ER1 tilts by a deflection angle THETA from the semi-polar principal surface SF of a second region ER2, and a force is thereby generated in the first region ER1 in a direction opposite to the direction of travel of the blade 5g toward the first region ER1.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: May 19, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Shimpei Takagi
  • Publication number: 20150129915
    Abstract: A method for manufacturing a light-emitting diode is provided. First, a substrate having a front or top surface and a rear or bottom surface is provided. An uneven pattern is formed on the rear or bottom surface. A light-emitting semiconductor layer is formed by stacking a first semiconductor layer, an active layer, and a second semiconductor layer on the front or top surface of the substrate having the uneven pattern. The light-emitting semiconductor layer and the substrate are separated into a plurality of light-emitting cells.
    Type: Application
    Filed: April 15, 2013
    Publication date: May 14, 2015
    Applicant: Seoul Viosys Co., Ltd.
    Inventors: ChungHoon Lee, DaeSung Cho, KiBum Nam
  • Patent number: 9029902
    Abstract: A semiconductor device includes a radiation-emitting semiconductor chip, a carrier substrate and a film. The carrier substrate has electrically conductive contact tracks on a top side. The film is arranged on a radiation exit side of the chip, the radiation exit side being remote from the carrier substrate, and on the top side of the carrier substrate and has electrically conductive first conductor tracks. The film has perforations arranged such that the semiconductor chip can be electrically contact-connected to the first contact track of the carrier substrate via the first conductor track of the film.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: May 12, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Magnus Ahlstedt, Johann Ramchen
  • Publication number: 20150118775
    Abstract: A method of manufacturing a nitride semiconductor element includes preparing a wafer having a nitride semiconductor layer which includes p-type dopants, forming an altered portion by condensing laser beam on the wafer, and after the forming an altered portion, forming a p-type nitride semiconductor layer by subjecting the wafer to annealing.
    Type: Application
    Filed: October 29, 2014
    Publication date: April 30, 2015
    Applicant: NICHIA CORPORATION
    Inventors: Junya NARITA, Yohei WAKAI, Kazuto OKAMOTO, Mizuki NISHIOKA
  • Publication number: 20150102304
    Abstract: A method of cutting an organic light-emitting display panel substrate into OLED display panels is disclosed. In one aspect, the method includes forming a plurality of OLEDs over a lower mother substrate, wherein the OLEDs are divided into a plurality of groups. The method also includes forming a plurality of sealant lines over at least one of an upper mother substrate or the lower mother substrate such that each sealant line surrounds a corresponding group of the OLEDs. The method further includes forming a plurality of assistance sealant lines between adjacent sealant lines, attaching the upper mother substrate to the lower mother substrate with the sealant lines and the assistance sealant lines interposed therebetween, and cutting the upper mother substrate and the lower mother substrate along the assistance sealant lines.
    Type: Application
    Filed: July 9, 2014
    Publication date: April 16, 2015
    Inventor: Jae Kyung GO
  • Patent number: 9006865
    Abstract: In heteroepitaxially growing a group-III nitride semiconductor on a Si single crystal substrate, the occurrence of cracks initiating in the wafer edge portion can be suppressed. Region A is an outermost peripheral portion outside the principal surface, being a bevel portion tapered. Regions B and C are on the same plane (the principal surface), region B (mirror-surface portion) being the center portion of the principal surface, and region C a region in the principal surface edge portion surrounding region B. The principal surface has a plane orientation, and in region B, is mirror-surface-finished. Region B occupies most of the principal surface of this Si single crystal substrate, and a semiconductor device is manufactured therein. Region C (surface-roughened portion) has a plane orientation as with region B, however, region B is mirror-surface-finished, whereas region C is surface-roughened.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: April 14, 2015
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Daisuke Hino, Tomohiko Shibata
  • Patent number: 9000434
    Abstract: A semiconductor device including a semiconductor substrate having a surface including an active semiconductor device including one of a laser and a photodiode; and a visual indicator disposed on the semiconductor body and at least adjacent to a portion of said active semiconductor device, the indicator having a state that shows if damage to the active semiconductor device may have occurred.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: April 7, 2015
    Assignee: Emcore Corporation
    Inventors: Richard Carson, Elaine Taylor, Douglas Collins
  • Patent number: 8999816
    Abstract: Approaches for protecting a wafer during plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer with a front surface having a plurality of integrated circuits thereon involves laminating a pre-patterned mask on the front surface of the semiconductor wafer. The pre-patterned mask covers the integrated circuits and exposes streets between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the streets to singulate the integrated circuits. The pre-patterned mask protects the integrated circuits during the plasma etching.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: April 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: James M. Holden, Aparna Iyer, Brad Eaton, Ajay Kumar
  • Patent number: 8999737
    Abstract: Methods of packaging a light emitting diode (LED) include providing a first lead having a first recess in a bottom surface and a second lead having a second recess in a bottom surface, placing a LED die over a top surface of at least one of the first and the second leads, electrically connecting the LED die to the first lead and to the second lead, forming a package around the LED die that includes an opening in its upper surface exposing at least the LED die, and separating the package containing the LED die, the first lead and the second lead from a lead frame such that the package contains a first castellation and a second castellation in a side surface of the package, such that the castellations expose the leads and/or a first platable metal which is electrically connected to the leads.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 7, 2015
    Assignee: Glo AB
    Inventors: Douglas Harvey, Ronald Kaneshiro
  • Publication number: 20150093844
    Abstract: Provided is a method of fabricating a light-emitting diode (LED) device. A wafer is provided. The wafer has a sapphire substrate and a semiconductor layer formed on the sapphire substrate. The semiconductor layer contains a plurality of un-separated LED dies. A photo-sensitive layer is formed over the semiconductor layer. A photolithography process is performed to pattern the photo-sensitive layer into a plurality of patterned portions. The patterned portions are separated by a plurality of openings that are each substantially aligned with one of the LED dies. A metal material is formed in each of the openings. The wafer is radiated in a localized manner such that only portions of the wafer that are substantially aligned with the openings are radiated. The sapphire substrate is removed along with un-radiated portions of the semiconductor layer, thereby separating the plurality of LED dies into individual LED dies.
    Type: Application
    Filed: December 11, 2014
    Publication date: April 2, 2015
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Gordon Kuo
  • Patent number: 8987024
    Abstract: System for wafer-level phosphor deposition. In an aspect, a semiconductor wafer is provided that includes a plurality of LED dies wherein at least one die includes an electrical contact, a photo-resist post covering the electrical contact, and a phosphor deposition layer covering the semiconductor wafer and surrounding the photo-resist post. In another aspect, a semiconductor wafer is provided that comprises a plurality of LED dies wherein at least one die comprises an electrical contact, a phosphor deposition layer covering the semiconductor wafer, and a cavity in the phosphor deposition layer exposing the at least one electrical contact.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: March 24, 2015
    Assignee: Bridgelux, Inc
    Inventor: Tao Xu
  • Patent number: 8989530
    Abstract: An array of optical devices includes singlets diced or separated from a first diced surface and a second diced surface of a semiconductor wafer. Each singlet includes a single optical emitter or a single photosensitive semiconductor device. The singlets are identified as operationally fit before being arranged in corresponding features in a receiving region of a submount. The corresponding features of the submount are arranged to align and precisely control the pitch or separation distance between optical portions of a desired number of singlets. The use of operationally fit singlets dramatically increases production efficiency as it is no longer necessary to identify N contiguous operational optical devices in a semiconductor wafer to produce a precisely aligned array of N operational optical devices.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: March 24, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Seng-Kum Chan
  • Patent number: 8987020
    Abstract: A method for manufacturing a semiconductor light-emitting device includes forming a multilayer body including a first semiconductor layer having a first major surface and a second major surface which is an opposite side from the first major surface, a second semiconductor layer including a light-emitting layer laminated on the second major surface of the first semiconductor layer, and electrodes formed on the second major surface of the first semiconductor layer and on a surface of the second semiconductor layer on an opposite side from the first semiconductor layer. The method includes forming a groove through the first semiconductor layer. The method includes forming a phosphor layer on the first major surface and on a side surface of the first semiconductor layer in the groove.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Yoshiaki Sugizaki
  • Publication number: 20150076476
    Abstract: A method of manufacturing an organic electroluminescent display device includes the steps of: forming a first insulating layer on a substrate; forming a first patterning layer; forming a second patterning layer; forming a trench portion; and forming an electrode layer on the second patterning layer and in the trench portion, wherein in the step of forming the trench portion, an end of the first patterning layer exposed within the trench portion is etched to an outside more than an end of the second patterning layer exposed within the trench portion in a plan view, and in the step of forming the electrode layer, the electrode layer formed within the trench portion is isolated from the electrode layer formed outside of the trench portion.
    Type: Application
    Filed: September 18, 2014
    Publication date: March 19, 2015
    Inventors: Kazuhiro ODAKA, Toshihiro SATO, Naoki TOKUDA
  • Patent number: 8975096
    Abstract: A jig includes a wafer including an accommodation groove configured to accommodate a capacitive micromachined ultrasonic transducer (cMUT) when flip chip bonding is performed, and a separation groove formed in a bottom surface of the accommodation groove, the separation groove having a bottom surface that is spaced apart from thin films of the cMUT that face the bottom surface of the separation groove when the cMUT is seated on portions of the bottom surface of the accommodation groove.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: March 10, 2015
    Assignees: Samsung Electronics Co., Ltd., Kyungpook National University Industry-Academic Cooperation Foundation
    Inventors: Young Il Kim, Bae Hyung Kim, Jong Keun Song, Seung Heun Lee, Kyung Il Cho, Yong Rae Roh, Won Seok Lee
  • Patent number: 8976829
    Abstract: An edge-emitting semiconductor laser is specified. A semiconductor body includes an active zone suitable for producing electromagnetic radiation. At least two facets on the active zone form a resonator. At least two contact points are spaced apart from one another in a lateral direction by at least one intermediate region and are mounted on an outer face of the semiconductor body.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: March 10, 2015
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Harald Koenig, Uwe Strauss, Wolfgang Reill
  • Publication number: 20150064823
    Abstract: A method for manufacturing a light emitting element that includes preparing a wafer having a substrate and a semiconductor structure, the substrate including a plurality of protrusions at positions corresponding to lattice points on a triangular lattice. The method includes forming a plurality of first modified parts in the substrate by irradiating the substrate with a laser beam along first dividing lines, forming a plurality of second modified parts in the substrate by irradiating the substrate with a laser beam along second dividing lines, and dividing the wafer along the first modified parts and the second modified parts to obtain a plurality of light emitting elements.
    Type: Application
    Filed: August 22, 2014
    Publication date: March 5, 2015
    Inventors: Hiroaki TAMEMOTO, Chihiro JUASA
  • Publication number: 20150060888
    Abstract: A method for fabricating an epitaxial structure includes providing a wafer comprising one or more epitaxial layers. The wafer is divided into dice where the area between the dice are called streets. Each street has a slot formed on either side of the street. The slots penetrate through the epitaxial layer but not the substrate leaving a portion of the epitaxial layer intact between the slots creating a “W” shaped cross section. A protective layer is then formed on the wafer. A laser may be used to singulate the wafer in to individual dice. The laser divides each street between the slots. The barrier walls of the epitaxial layers protect the individual dice from debris created by laser separation.
    Type: Application
    Filed: April 5, 2013
    Publication date: March 5, 2015
    Inventors: Songnan Wu, Boris Kharas
  • Publication number: 20150064824
    Abstract: An optical device including a substrate formed of a light transmitting material and a light emitting layer formed on the front surface of the substrate. Both the front surface and the back surface of the substrate are parallel to each other and have substantially the same rectangular shape. The substrate has four side surfaces connecting the front surface and the back surface of the substrate. Each side surface of the substrate has a corrugated sectional shape such that a plurality of concave portions and convex portions are alternately formed.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Inventor: Kota Fukaya
  • Patent number: 8969175
    Abstract: A method for producing singulated semiconductor components includes providing a starting substrate. An etching process is carried out to form depressions at a side of the starting substrate. The depressions are arranged in the region of the semiconductor components to be produced. Walls present between the depressions are arranged in the region of separating regions provided for severing the starting substrate. The method furthermore comprises forming a metallic layer on the side of the starting substrate with the depressions and walls and carrying out a further etching process for severing the starting substrate in the separating regions and forming the singulated semiconductor components.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: March 3, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Andreas Ploessl, Heribert Zull
  • Publication number: 20150056730
    Abstract: The present invention relates to a semiconductor device, a manufacturing method thereof. More specifically, this invention is related to a chemical etching method in semiconductor device separation process without using dicing or scribing. According to an example of the invention, a method for manufacturing a semiconductor device, the method comprising: forming a light emitting semiconductor device layer that emits light by current injection; and forming at least one metal layer with etch barrier plated thereon on the semiconductor device layer, wherein the at least one metal layer provides mechanical support to the semiconductor device, wherein the etch barrier is plated on the at least one metal layer in a direction that the etch barrier can prevent side wall under-cut when the street lines are separated by wet chemical etching.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 26, 2015
    Inventors: Kyu Sung Hwang, Se Jong Oh, Myung Cheol Yoo, Moo Keun Park, Sang Don Lee
  • Publication number: 20150054017
    Abstract: An LED chip package having a topographical glass coating on top surface for enhancing heat dissipation is disclosed. A circular wall is optionally built to surround the LED chip for reflecting light beams from the LED chips; the glass coating further extends to cove the inner wall surface of the circular wall. The larger area the glass coating covers, the more heat the package dissipates in a time unit. The LED chip package according to the present invention exhibits higher thermal dissipation and helps to last longer the life of the LED chip package than a traditional one.
    Type: Application
    Filed: August 20, 2013
    Publication date: February 26, 2015
    Applicant: Prolight Opto Technology Corporation
    Inventors: Chen-Lun HSING CHEN, Chien-Cheng KUO, Jung-Hao HUNG, Cheng-Chung LEE, Ding-Yao LIN, Meng-Chi LI, Ping-Chun TSAI
  • Patent number: 8962363
    Abstract: Provided is a novel method for forming a groove composed of two smooth inclined surfaces on a surface of a flat plate formed of a nitride semiconductor crystal having an A, C, M-axes. In the present invention, a disk-shaped dicing blade is moved along a direction of the A-axis to form first and second inclined surfaces on the surface of the flat plate. The following mathematical formulae (I)-(III) are satisfied: 45 degrees??b?a?60 degrees (I) 45 degrees??b+a?60 degrees (II), 0 degrees?|a|?7.5 degrees, where angle ?b represents an angle formed between a surface of the edge and a radial direction of the dicing blade in a cross-sectional view which includes the M-axis and the C-axis. The angle a represents an angle formed between the principal surface and the M-axis.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 24, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Akira Inoue, Toshiyuki Fujita, Toshiya Yokogawa
  • Patent number: 8962362
    Abstract: A method for manufacturing vertically structured Group III nitride semiconductor LED chips includes a step of forming a light emitting laminate on a growth substrate; a step of forming a plurality of separate light emitting structures by partially removing the light emitting laminate to partially expose the growth substrate; a step of forming a conductive support on the plurality of light emitting structures; a step of lifting off the growth substrate from the plurality of light emitting structures; and a step of cutting the conductive support thereby singulating a plurality of LED chips each having the light emitting structure. The step of partially removing the light emitting laminate is performed such that each of the plurality of light emitting structures has a top view shape of a circle or a 4n-gon (“n” is a positive integer) having rounded corners.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: February 24, 2015
    Assignees: Wavesquare Inc., Dowa Electronics Materials Co., Ltd.
    Inventors: Meoung Whan Cho, Seog Woo Lee, Pil Guk Jang, Ryuichi Toba, Tatsunori Toyota, Yoshitaka Kadowaki
  • Publication number: 20150050765
    Abstract: A photolithographic method which produces a structure in a radiation-emitting semiconductor component by providing a semiconductor wafer having a semiconductor layer sequence, applying a first photoresist layer to the semiconductor wafer, providing a mask, and arranging the mask relative to the coated semiconductor wafer, exposing the first photoresist layer and imaging the mask in the first photoresist layer, arranging the mask or a different mask relative to the semiconductor wafer at another position different from a first position and again exposing the first photoresist layer and imaging the mask in the first photoresist layer or applying a second photoresist layer to the first photoresist layer, arranging the mask or a different mask relative to the semiconductor wafer at a second position, and exposing the second photoresist layer and imaging the mask in the second photoresist layer, forming a patterned photoresist layer and patterning the semiconductor wafer.
    Type: Application
    Filed: August 15, 2014
    Publication date: February 19, 2015
    Inventors: Bernd Böhm, Sebastian Hoibl
  • Patent number: 8956887
    Abstract: The invention is directed to the provision of a method for manufacturing a semiconductor light-emitting element that eliminates the need for preparing a plurality of different fluorescent sheets. The method for manufacturing the semiconductor light-emitting element containing an LED die includes the steps of arranging the LED die on a fluorescent sheet containing a fluorescent substance and adjusting the amount by which the LED die is depressed into the fluorescent sheet so that the semiconductor light-emitting element has a desired color emission.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: February 17, 2015
    Assignees: Citizen Holdings Co., Ltd., Citizen Electrinocs Co., Ltd.
    Inventor: Kazuaki Sorimachi
  • Patent number: 8956901
    Abstract: An integral LED component is mounted into a hollow carrier. The carrier has two conductive electrodes with opposite polarities. The LED component comprises a substrate, N number of LED epitaxial structures where N is a number greater than one, a third electrode and a fourth electrode. The N number of LED epitaxial structures are formed on the upper surface of the substrate, the at least one of the N number of LED epitaxial structures comprises a first and a second electrode. The third and fourth electrodes are formed on the upper surface and located outside the N number of LED epitaxial structures, the respective electrodes are electrically connected to form a circuit. The two conductive electrodes of the hollow carrier are used for electrically connecting the third and fourth electrodes of the substrate, and the lower surface of the substrate is exposed to the hollow carrier.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: February 17, 2015
    Inventor: Jen-Shyan Chen