Abstract: The actinic ray-sensitive or radiation-sensitive resin composition according to the present invention includes a resin (A) which contains at least one type of repeating unit which is represented by the general formula (PG1), at least one type of repeating unit which is selected from the repeating units which are represented by the general formula (PG2) and the general formula (PG3), and at least one type of repeating unit which includes a lactone structure, a compound (B) which is a compound which is represented by the general formula (B1) and where the molecular weight of an anion moiety is 200 or less, and a solvent (C).

Abstract: A power semiconductor device and a manufacturing method thereof are provided. The method of manufacturing a power semiconductor device includes the steps: (a) forming a cell structure on a first conductivity type semiconductor substrate; (b) implanting second conductivity type ions onto the rear surface of the first conductivity type semiconductor substrate and activating to form an electrode region; and (c) implanting ions creating first conductivity type with a doping concentration higher than that of the semiconductor substrate and activating to form a high-concentration ion implanted region at a position below the cell structure and on the electrode region. Accordingly, it is possible to form a field stop layer regardless of conditions for forming an electrode region (for example, a P-type collector region) and thus to optimize stable breakdown voltage characteristics and device characteristics.

Abstract: A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to foil the features on the target layer. A partially fabricated integrated circuit device is also disclosed.

Abstract: Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.

Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a low refractive index layer. The first semiconductor layer has a first major surface and a second major surface being opposite to the first major surface. The light emitting layer has an active layer provided on the second major surface. The second semiconductor layer is provided on the light emitting layer. The low refractive index layer covers partially the first major surface and has a refractive index lower than the refractive index of the first semiconductor layer.

Abstract: A semiconductor structure comprises a substrate and a metal layer disposed over the substrate. The metal layer comprises a first electrical trace and a second electrical trace. The semiconductor structure comprises a conductive pillar disposed directly on and in electrical contact with the first electrical trace; and a dielectric layer selectively disposed between the metal layer and the conductive pillar. The dielectric layer electrically isolates the second electrical trace from the pillar.

Abstract: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.

Abstract: A semiconductor device structure, for improving the metal gate leakage within the semiconductor device. A structure for a metal gate electrode for a n-type Field Effect Transistor includes a capping layer; a first metal layer comprising Ti and Al over the capping layer; a metal oxide layer over the first metal layer; a barrier layer over the metal oxide layer; and a second metal layer over the barrier layer.

Abstract: A semiconductor memory device includes a plurality of active pillars protruding from a semiconductor substrate, a first gate electrode disposed on at least one sidewall of the active pillar, a first gate insulating layer being disposed between the active pillar and the first gate electrode, a second gate electrode disposed on at least one sidewall of the active pillar over the first gate electrode, a second gate insulating layer being disposed between the active pillar and the second gate electrode, first and second body regions in the active pillar adjacent to respective first and second respective electrodes, and first through third source/drain regions in the active pillar arranged alternately with the first and second body regions.

Abstract: A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers.

Abstract: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.

Abstract: The embodiments of mechanisms described enables improved planarity of substrates, which is crucial for patterning and device yield improvement. Chemical-mechanical polishing (CMP) is used to remove film to planarize the substrate before the final thickness is reached or before all removal film is polished. The substrate is then measured for its topography and film thickness. The topography and thickness data are used by the gas cluster ion beam (GOB) etch tool to determine how much film to remove on a particular location. GOB etch enables removal of final layer to meet the requirements of substrate uniformity and thickness target. The mechanisms enable improved planarity to meet the requirement of advanced processing technologies.

Abstract: A semiconductor storage device according to an embodiment comprises active areas on a semiconductor substrate. An element isolation is arranged between the active areas and filled by an insulating film. A plurality of memory cells configured to store data are formed on the active areas. Air gaps are arranged between upper-end edge parts of the active areas where the memory cells are formed and an insulating film in the element isolation.

Abstract: An antireflective coating that contains at least two polymer components and comprises chromophore moieties and transparent moieties is provided. The antireflective coating is useful for providing a single-layer composite graded antireflective coating formed beneath a photoresist layer.

Abstract: Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

Abstract: A method of modifying a fluorinated polymer surface comprising the steps of depositing a first layer on at least a portion of the fluorinated polymer surface, the first layer comprising a first polymer, the first polymer being a substantially perfluorinated aromatic polymer; and depositing a second layer on at least a portion of the first layer, the second layer comprising a second polymer, the second polymer being an aromatic polymer having a lower degree of fluorination than said first polymer, whereby the second layer provides a surface on to which a substance having a lower degree of fluorination than the first polymer, e.g. a non-fluorinated substance is depositable.

Abstract: A semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contact plugs extending in the stack direction of the cell array layers to connect between the first lines, between the second lines, between the first or second line and the semiconductor substrate, or between the first or second line and another metal line, in the cell array layers. The first or second line in a certain one of the cell array layers has a contact connector making contact with both sides of the contact plug.

Abstract: A device (20, 90) includes sensors (28, 30) that sense different physical stimuli. A pressure sensor (28) includes a reference element (44) and a sense element (52), and an inertial sensor (30) includes a movable element (54). Fabrication (110) entails forming (112) a first substrate structure (22, 92) having a cavity (36, 100), forming a second substrate structure (24) to include the sensors (28, 30), and coupling (128) the substrate structures so that the first sensor (28) is aligned with the cavity (36, 100) and the second sensor (30) is laterally spaced apart from the first sensor (28). Forming the second structure (24) includes forming (118) the sense element (52) from a material layer (124) of the second structure (24) and following coupling (128) of the substrate structures, concurrently forming (132) the reference element (44) and the movable element (54) in a wafer substrate (122) of the second structure (24).

Abstract: A graphene-based memristor includes a first electrode, a defective graphene layer adjacent the first electrode, a memristive material that includes a number of ions adjacent the defective graphene layer, a second electrode adjacent the memristive material, and a voltage source that generates an electric field between the first and the second electrodes. Under the influence of the electric field, ions in the memristive material form an ion conducting channel between the second electrode and the defective graphene layer.

Abstract: An overlay vernier mask pattern of a semiconductor device includes a first overlay vernier mask pattern having a first opening for exposing a first area of a layer to be etched on a substrate and a second opening for exposing a second area spaced apart from the first area, and a second overlay vernier mask pattern aligned on the first overlay vernier mask pattern and the layer to be etched, and having an opening for exposing the second opening while exposing a portion of the layer to be etched in the first area.

Abstract: A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.

Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Abstract: A micro-electro-mechanical systems (MEMS) package includes a MEMS microphone device. The MEMS microphone device has a first substrate and at least a sensing element on the first substrate wherein a first chamber in the MEMS microphone device is connected to the sensing element. A second substrate is disposed over the MEMS microphone device to provide a second chamber in the second substrate over the sensing element opposite to the first chamber.

Abstract: A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; a well region, a first N+ diffusion region, a first P+ diffusion region, a second N+ diffusion region, a second P+ diffusion region, a third P+ diffusion region, positioned in one side of the DTSCR and across the well region and semiconductor substrate; a third N+ diffusion region, positioned in another side of the DTSCR and across the well region and the semiconductor substrate; a first gate, positioned above the semiconductor substrate between the first P+ diffusion region and the third P+ diffusion region, utilized as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the well region between the second N+ diffusion region and the third N+ diffusion region, utilized as an N-type trigger node to receive a second trigger current or a second trigger voltage.

Abstract: Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example.

Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of the surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.

Abstract: Back-end-of-line (BEOL) wiring structures that include an on-chip inductor and an on-chip capacitor, as well as design structures for a radiofrequency integrated circuit. The on-chip inductor and an on-chip capacitor, which are fabricated as conductive features in different metallization levels, are vertically aligned with each other. The on-chip capacitor, which is located between the on-chip inductor and the substrate, may serve as a Faraday shield for the on-chip inductor. Optionally, the BEOL wiring structure may include an optional Faraday shield located vertically either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the top surface of the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the electrodes of the on-chip capacitor to permit tuning, during circuit operation, of a resonance frequency of an LC resonator that further includes the on-chip inductor.

Abstract: A semiconductor die includes a substrate, a first device region and a second device region. The first device region includes an epitaxial layer on the substrate and one or more semiconductor devices of a first type formed in the epitaxial layer of the first device region. The second device region is spaced apart from the first device region and includes an epitaxial layer on the substrate and one or more semiconductor devices of a second type formed in the epitaxial layer of the second device region. The epitaxial layer of the first device region is different than the epitaxial layer of the second device region so that the one or more semiconductor devices of the first type are formed in a different epitaxial layer than the one or more semiconductor devices of the second type.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type on the semiconductor substrate, and a plurality of second semiconductor regions of a second conductivity type disposed separately in the first semiconductor region. A difference between a charge quantity expressed by an integral value of a net activated doping concentration in the second semiconductor regions in the surface direction of the semiconductor substrate and a charge quantity expressed by an integral value of a net activated doping concentration in the first semiconductor region in the surface direction of the semiconductor substrate is always a positive quantity and becomes larger from the depth of the first junction plane to a depth of a second junction plane on an opposite side from the first junction plane.

Abstract: The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are placed on the MOSFET such that the distances between drains, sources, and gates are optimized to reduce resistance and power dissipation. The gates may be arranged in a trapezoidal arrangement in order to maximize a ratio of the gate widths to gate lengths for current driving while reducing resistance and power dissipation.

Abstract: The present invention relates to an electronic device comprising at least one dielectric layer, said dielectric layer comprising a crosslinked organic compound based on at least one compound which is radically crosslinkable and a method of making the electronic device.

Abstract: An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. An isolated junction field-effect transistor is formed in the isolated pocket.

Abstract: A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.

Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.

Abstract: An inductor includes a first air-bridge section and a second air-bridge section. The first air-bridge unit extends in a floating location over a substrate between a plurality of support locations on the substrate. The second air-bridge unit extends in a floating location over the first air-bridge unit between a plurality of support locations on the first air-bridge unit. This arrangement enables the first and second air-bridge sections to be connected in parallel, thus branching a flowing current. Thus, the conductor loss in each of the first and second air-bridge sections is reduced.

Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.

Abstract: A low cost passive RFID tag uses capacitive or inductive coupling between the RF IC chip and the antenna. Coupling elements are formed directly on the surface of the RF IC chip.

Abstract: A circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead. Where one of the dies contains vertical circuit element, where a doped layer forms a terminal along the bottom surface of the layer, a trench filled with doped polysilicon extends from the top surface to the terminal to connect to the terminal.

Abstract: Provided is a manufacturing method of a semiconductor device, which is capable of realizing fine-pitch patterns and thus improving stabilization of patterning precision. The manufacturing method of the semiconductor device comprises forming a first photoresist pattern in a predetermined region on a substrate, depositing a thin film on the surface of the first photoresist pattern, and forming a second photoresist pattern in a region where the first photoresist pattern is not formed.

Abstract: A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region, a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second P+ diffusion region and the third P+ diffusion region, for use as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first N+ diffusion region and the third N+ diffusion region, for use as an N-type trigger node to receive a second trigger current or a second trigger voltage.

Abstract: A power semiconductor device is provided that includes a depletion mode (normally ON) main switching device cascoded with a higher speed switching device, resulting in an enhancement mode (normally OFF) FET device for switching power applications. The main switching device comprises a depletion mode GaN-based HEMT (High Electron Mobility Transistor) FET that does not include an intrinsic body diode. In one or more embodiments, the higher speed switching device comprises a high speed FET semiconductor switch arranged or connected in parallel with a Schottky diode. The high speed FET semiconductor switch may comprise a Si FET, GaN FET or any other type of FET which possesses higher speed switching capabilities and a lower voltage than that of the GaN-based HEMT FET. In some embodiments, the GaN-based HEMT FET and the higher speed switching device (i.e., the FET and Schottky diode) may be monolithically integrated on the same substrate.

Abstract: A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.

Abstract: An improvement for a smart, highside, high current, power switch module formed in an integrated circuit having at least one composite MOS/FET transistor switch connected to controlling and protection circuits. The power switch module has a load terminal (L), a battery input terminal (B), a control input terminal (C) and a diagnostic feedback terminal (M). The improvement provides overcurrent protection from a substantially instantaneous short circuit across an electrical load connected to the load terminal of the power switch module. The improvement is a capacitive circuit element connected between the battery input terminal (B) and the diagnostic feedback terminal (M).

Abstract: A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain creating fin region. The first semiconductor seed region is sandwiched between the first strain creating fin region and the dielectric layer. The first semiconductor seed region includes a first semiconductor material. The first strain creating fin region includes the first semiconductor material and a second semiconductor material different than the first semiconductor material. A first atom percent of the first semiconductor material in the first semiconductor seed region is different than a second atom percent of the first semiconductor material in the first strain creating fin region.

Abstract: Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrate and that contains a source region, a drain region, and a channel region, a charge reserving layer formed on the channel region, and a gate formed on the substrate to contact the channel region and the charge reserving layer.

Abstract: A semiconductor device includes: a first well and a second well formed in a substrate and having a different impurity doping concentration; a first isolation layer and a second isolation layer formed in the first well and the second well, respectively, and having a different depth; and a third isolation layer formed in a boundary region in which the first well and the second well are in contact with each other, and having a combination type of the first isolation layer and the second isolation layer.

Abstract: A magnetic stack with a multilayer free layer having a switchable magnetization orientation, the free layer comprising a first ferromagnetic portion and a second ferromagnetic portion with an electrically conducting non-magnetic intermediate layer between the first portion and the second portion. The magnetic stack also includes a first ferromagnetic reference layer having a pinned magnetization orientation, a first non-magnetic spacer layer between the free layer and the first reference layer, a second ferromagnetic reference layer having a pinned magnetization orientation, and a second non-magnetic spacer layer between the free layer and the second reference layer.

Abstract: A nitride semiconductor device according to the present invention includes a Group III nitride semiconductor; and an insulating film containing oxygen formed on the surface of the Group III nitride semiconductor, wherein the nitrogen concentration in a region provided with the insulating film is higher than the nitrogen concentration in a region not provided with the insulating film on the surface of the group III nitride semiconductor.

Abstract: Methods, systems, and devices which result from, or facilitates, convenient processing of partial dies of a semiconductor chip in a lithography process are disclosed. Embodiments utilize an exposure through an imprint-style template which does not come in physical contact with the partial die. In one embodiment, a semiconductor process is disclosed which has at least one full die and at least one partial die. The semiconductor chip is fabricated, in part, by using an etching process which utilizes an imprint template configured to be exposed to the at least one full die when the imprint template is in contact with resist which has been dispensed onto the at least one full die. Further, at least one partial die of the semiconductor chip is configured to be exposed to the imprint template without the template contacting resist dispensed onto the at least one partial die.