Patents Examined by Bradley Smith
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Patent number: 12295192Abstract: In an embodiment a method for producing a component having a carrier and at least one component part electrically conductively connected to the carrier and mechanically fixed to the carrier by an electrically insulating bonding layer includes providing the carrier having a connection layer, wherein the bonding layer is disposed on the carrier and has at least one opening, wherein a connection surface of the connection layer is exposed, and wherein the bonding layer projects vertically beyond the exposed connection surface or vice versa, applying the component part having a contact layer on the carrier in such that, in top view of the carrier, an exposed contact surface of the contact layer covers the opening and the connection surface located therein, wherein the exposed contact surface is spaced apart from the exposed connection surface by a vertical distance and reducing the vertical distance by changing a volume of the bonding layer such that the exposed contact surface and the exposed connection surface aType: GrantFiled: May 6, 2020Date of Patent: May 6, 2025Assignee: OSRAM Opto Semiconductors GmbHInventors: Alexander F. Pfeuffer, Tobias Berthold, Lutz Höppel, Tobias Meyer, Korbinian Perzlmaier
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Patent number: 12288800Abstract: A monolithic semiconductor LED display system comprising a layered semiconductor material system fabricated to form a plurality of light emitting switch devices. Each of the light emitting switch devices extends along a different axis from a common substrate and comprises a driver device and a light emitting diode. Each of the driver devices comprises, in adjacent order from the substrate and in series, a first type of doped region, a second type of doped region and another of the first type of doped region. Areas of the layered semiconductor material system not utilized for the LED elements are fabricated to form circuitry in two or more of the doped regions for each of the light emitting switch devices.Type: GrantFiled: November 16, 2021Date of Patent: April 29, 2025Assignee: INNOVATION SEMICONDUCTORInventor: Matthew T. Hartensveld
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Patent number: 12278139Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.Type: GrantFiled: August 1, 2023Date of Patent: April 15, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
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Patent number: 12249676Abstract: A display device includes a substrate, a plurality of pixels, a light emitting element, and an inorganic insulating layer. The pixels are provided to the substrate. The light emitting element is provided to each of the pixels. The inorganic insulating layer has translucency and covers at least part of the light emitting element. The inorganic insulating layer includes a side part and an extending part. The side part is provided to the side surface of the light emitting element. The extending part is provided at a side on the lower end of the side part and extending toward the outer side of the light emitting element than the side part in planar view seen from the normal direction of the substrate.Type: GrantFiled: May 11, 2021Date of Patent: March 11, 2025Assignee: Japan Display Inc.Inventors: Osamu Itou, Masanobu Ikeda, Masataka Ikeda
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Patent number: 12225788Abstract: A display device includes: a substrate including a display area and a peripheral area positioned outside the display area; a first power supply line positioned in the peripheral area; a first insulating layer positioned on the first power supply line; and a second power supply line positioned on the first insulating layer in the peripheral area. The first power supply line includes a first main wire extending in a first direction and a first sub-wire diverging toward the display area from the first main wire, the second power supply line includes a second main wire extending in the first direction and a second sub-wire diverging toward the display area from the second main wire, the first main wire includes an internal edge positioned near the first sub-wire and an external edge facing the internal edge, and the second main wire does not overlap the internal edge in a plan view.Type: GrantFiled: October 21, 2021Date of Patent: February 11, 2025Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Yong Duck Son, Yul Kyu Lee, Min-Sik Jung, Jun Hwi Park
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Patent number: 12218007Abstract: A method includes forming a first mandrel and a second mandrel over a dielectric layer, and forming a first spacer and a second spacer on the first mandrel and the second mandrel, respectively. The first spacer and the second spacer are next to each other with a space in between. The dielectric layer is etched to form an opening in the dielectric layer, with the opening being overlapped by the space, and with the first spacer and the second spacer being used as a part of an etching mask in the etching. A conductive material is filled into the opening. A planarization process is performed on the conductive material.Type: GrantFiled: June 7, 2021Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Nien Su, Jyu-Horng Shieh
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Patent number: 12217192Abstract: Various systems and methods of initiating and performing contextualized AI inferencing, are described herein. In an example, operations performed with a gateway computing device to invoke an inferencing model include receiving and processing a request for an inferencing operation, selecting an implementation of the inferencing model on a remote service based on a model specification and contextual data from the edge device, and executing the selected implementation of the inferencing model, such that results from the inferencing model are provided back to the edge device. Also in an example, operations performed with an edge computing device to request an inferencing model include collecting contextual data, generating an inferencing request, transmitting the inference request to a gateway device, and receiving and processing the results of execution. Further techniques for implementing a registration of the inference model, and invoking particular variants of an inference model, are also described.Type: GrantFiled: December 30, 2022Date of Patent: February 4, 2025Assignee: Intel CorporationInventors: Francesc Guim Bernat, Suraj Prabhakaran, Kshitij Arun Doshi, Da-Ming Chiang, Joe Cahill
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Patent number: 12218004Abstract: A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base; forming a pattern memory layer on the base, where at least a first trench and a second trench are provided on the pattern memory layer, where an extending direction of the first trench is parallel to an extending direction of the second trench, and the first trench and the second trench are formed using different masks; and forming mandrel lines separated on the base at positions of the base that correspond to the first trench and the second trench. By using the method, a problem that a photoresist peels off during etching due to an elongated shape when separated mandrel lines are directly formed can be avoided. Further, a problem of a relatively high requirement on a filling material when the mandrel lines are formed directly by using a plurality of photolithography processes can be avoided, to lower the requirement on the filling material.Type: GrantFiled: April 13, 2021Date of Patent: February 4, 2025Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: He Zuopeng, Yang Ming, Bei Duohui
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Patent number: 12211717Abstract: A method includes identifying first structure data of a first region of a substrate and receiving optical metrology data of the substrate associated with one or more substrate deposition processes in a processing chamber. The method further includes determining, based on the optical metrology data and the first structure data, a first growth rate of the first region of the substrate associated with the one or more substrate deposition processes. The method further includes predicting, based on the optical metrology data and the first growth rate, thickness data of a second region of the substrate without second structure data of the second region.Type: GrantFiled: March 29, 2021Date of Patent: January 28, 2025Assignee: Applied Materials, Inc.Inventors: Eric Chin Hong Ng, Edward Wibowo Budiarto, Mehdi Vaez-Iravani, Todd Jonathan Egan, Venkatakaushik Voleti
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Patent number: 12199173Abstract: A nitride semiconductor device 1 includes a first nitride semiconductor layer 4 that constitutes an electron transit layer, a second nitride semiconductor layer 5 that is formed on the first nitride semiconductor layer, is larger in bandgap than the first nitride semiconductor layer, and constitutes an electron supply layer, and a gate portion 20 that is formed on the second nitride semiconductor layer. The gate portion 20 includes a first semiconductor gate layer 21 of a ridge shape that is disposed on the second nitride semiconductor layer 5 and is constituted of a nitride semiconductor containing an acceptor type impurity, a second semiconductor gate layer 22 that is formed on the first semiconductor gate layer 21 and is constituted of a nitride semiconductor with a larger bandgap than the first semiconductor gate layer 21, and a gate electrode 23 that is formed on the second semiconductor gate layer 22 and is in Schottky junction with the second semiconductor gate layer 22.Type: GrantFiled: January 15, 2020Date of Patent: January 14, 2025Assignee: ROHM CO., LTD.Inventors: Hirotaka Otake, Shinya Takado, Taketoshi Tanaka, Norikazu Ito
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Patent number: 12191336Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a substrate. A pixel region of the substrate is disposed within an inner perimeter of the DTI structure. A photodetector is disposed in the pixel region of the substrate. A gate electrode structure overlies, at least partially, the pixel region of the substrate. A first gate dielectric structure partially overlies the pixel region of the substrate. A second gate dielectric structure partially overlies the pixel region of the substrate. The gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness that is greater than the first thickness.Type: GrantFiled: May 23, 2022Date of Patent: January 7, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Jui Wang, Dun-Nian Yaung, Chen-Jong Wang, Ming-Chieh Hsu, Wei-Cheng Hsu, Yuichiro Yamashita
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Patent number: 12183846Abstract: The present disclosure relates to a device and method for removing metal gallium, and a laser lift-off system. The device includes a device body, and the device body includes a process chamber (10), wherein fluid used for removing metal gallium left on the surfaces of multiple Micro Light Emitting Diode (Micro-LED) chips after laser lift-off is contained in the process chamber (10); and a temperature of the fluid is greater than or equal to a melting point of metal gallium.Type: GrantFiled: June 16, 2020Date of Patent: December 31, 2024Assignee: CHONGQING KONKA PHOTOELECTRIC TECHNOLOGY RESEARCH INSTITUTE CO., LTD.Inventors: Chunlin Fan, Bin Wang, Qing Wang
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Patent number: 12166070Abstract: The present application discloses a semiconductor transistor structure, which includes: a substrate formed with a well region of a first conductive type, a gate structure being disposed on the substrate; a source/drain region of a second conductive type disposed in the well region of the first conductive type, the source region and the drain region being located on two sides of the gate structure respectively; a contact hole formed at a position corresponding to the source/drain region; and a conductive metal filled in the contact hole, the bottom of the contact hole being implanted with impurity ions for decreasing the contact resistance of the contact hole, and the impurity ion concentration at a peripheral region where the bottom of the contact hole comes into contact with the source/drain region being lower than the impurity ion concentration at a middle region.Type: GrantFiled: September 28, 2021Date of Patent: December 10, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jifeng Tang
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Patent number: 12165884Abstract: Discussed is a self-assembly apparatus for a plurality of semiconductor light-emitting devices, and a method for self-assembly of the plurality of semiconductor light-emitting devices, whereby the apparatus includes a chamber accommodating the plurality of semiconductor light-emitting devices and a fluid; a transferor to transfer a substrate to an assembly position; a magnet to apply a magnetic force to the plurality of semiconductor light-emitting devices; a position controller to control a position of the magnet; and a vibration generator in contact with the fluid to generate a vibration in the fluid to separate the plurality of semiconductor light-emitting devices from each other while in the fluid, wherein an electric field is produced in the substrate while the plurality of semiconductor light-emitting devices are moved according to a change of the position of the magnet.Type: GrantFiled: May 28, 2019Date of Patent: December 10, 2024Assignee: LG ELECTRONICS INC.Inventors: Hyunho Lee, Bongchu Shim, Gunho Kim
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Patent number: 12161028Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a first conductive pattern and a second conductive pattern arranged at different layers and electrically connected to each other via at least two conductive connection structures.Type: GrantFiled: May 25, 2020Date of Patent: December 3, 2024Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Tingliang Liu, Weiyun Huang, Xiangdan Dong, Yue Long
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Patent number: 12155004Abstract: The present disclosure relates to a method of separating a plurality of light-emitting diode (LED) structures from a wafer. According to the method, the LED structures each having a desired size, thickness, and shape can be separated from the wafer, using a commercialized wafer, without damage to the LED structures even without considering the presence or absence of a sacrificial layer and specifically pre-designing a thickness of semiconductor layers in the wafer from the time of wafer manufacturing.Type: GrantFiled: December 28, 2021Date of Patent: November 26, 2024Assignee: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATIONInventor: Young Rag Do
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Patent number: 12145349Abstract: A light emitting device can further improve light extraction efficiency. A method of manufacturing such a light emitting device can also prove advantageous. The light emitting device includes a light emitting element, a light-transmissive member which is disposed on a light extracting surface side of the light emitting element, and a reflecting layer disposed on an element bonding surface of the light transmissive member where the light emitting element is disposed and adjacent to the light emitting element. The light-transmissive member, in a plan view, has a planar dimension greater than the light extracting surface of the light emitting element.Type: GrantFiled: March 10, 2021Date of Patent: November 19, 2024Assignee: NICHIA CORPORATIONInventors: Daisuke Sanga, Masatsugu Ichikawa, Shunsuke Minato, Toru Takasone, Masahiko Sano
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Patent number: 12132142Abstract: A method of manufacturing a semiconductor element according to the present disclosure includes an element forming step (S1) of forming, on an underlying substrate (11), a semiconductor element (15) connected to the underlying substrate (11) via a connecting portion (13b) and including an upper surface (15a) inclined with respect to a growth surface of the underlying substrate (11), a preparing step (S2) of preparing a support substrate (16) including an opposing surface (16c) facing the underlying substrate (11), a bonding step (S3) of pressing the upper surface (15a) of the semiconductor element (15) against the opposing surface (16c) of the support substrate (16) and heating the upper surface (15a) to bond the upper surface (15a) of the semiconductor element (15) to the support substrate (16), and a peeling step (S4) of peeling the semiconductor element (15) from the underlying substrate (11).Type: GrantFiled: February 28, 2020Date of Patent: October 29, 2024Assignee: KYOCERA CORPORATIONInventors: Katsuaki Masaki, Kentaro Murakawa
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Patent number: 12119389Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; forming fins on the substrate; depositing a dummy gate electrode over the fins; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; performing a first treatment at a first temperature to repair defects in at least one of the dummy gate electrode, the gate spacer and the LDD region; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; depositing an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and subsequent to the forming of the replacement gate, performing a second treatment at a second temperature, lower than the first temperature, to repair defects of the semiconductor device.Type: GrantFiled: July 28, 2023Date of Patent: October 15, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hsiung Tsai, Kuo-Feng Yu, Yu-Ming Lin, Clement Hsingjen Wann
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Patent number: 12120871Abstract: A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first cell structure and the second cell structure, and may be electrically coupled to the first and second cell structures. The pad structure may have a plurality of stepped structures. The circuit may be disposed under the pad structure. The one or more openings may pass through the pad structure, and may expose the circuit. The one or more openings may be disposed between the plurality of stepped structures.Type: GrantFiled: January 20, 2021Date of Patent: October 15, 2024Assignee: SK hynix Inc.Inventor: Nam Jae Lee